1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to a test circuit and a redundancy circuit for an internal memory circuit.
2. Description of the Background Art
Among prior-art test circuits and redundancy circuits for a memory circuit in a semiconductor integrated circuit device is a test circuit and a redundancy circuit shown in Japanese Patent Application Laid-Open Gazette 8-94718.
FIG. 43 is a circuit diagram showing a configuration of a prior-art scan flip flop 200 (hereinafter, sometimes abbreviated as "S-FF") for a RAM test.
As shown in FIG. 43, a comparator 201 consists of an EX-OR gate 202 and a NAND gate 203. One of inputs of the EX-OR gate 202 receives input data D and the other receives expected value data EXP, and one of inputs of the NAND gate 203 is connected to an output of the EX-OR gate 202 and the other receives a comparison control signal CMP. An output of the NAND gate 203 serves as an output of the comparator 201.
The output of the comparator 201 is connected to one of inputs of an AND gate 204. A selector 205 has a "0"-input receiving a serial input (data ) SI, a "1"-input connected to an output of the AND gate 204 and a control input receiving a test-mode signal TM1. The selector 205 outputs a signal given from the "1"/"0"-input based on "1"/"0" of the test-mode signal TM1 through its output unit Y.
A selector 206 has a "0"-input receiving the input data D, and a "1"-input connected to the output unit Y of the selector 205 and a control input receiving a shift-mode signal SM. The selector 206 outputs a signal given from the "1"/"0" input based on "1"/"0" of the shift-mode signal SM through its output unit Y.
The D-FF (D-type flip flop) 207 has a D-input connected to the output unit Y of the selector 206, a toggle input T receiving a timing signal (clock signal) T and a Q-output for outputting signals. The signals from the output unit Q are given outside and fed back to the other input of the AND gate 204 as a data output Q and a serial output (data) SO.
In this configuration, with the shift-mode signal SM of "0", a normal operation starts to take the input data D into the D-FF 207 in synchronization with a timing signal T.
With the shift-mode signal SM of "1" and the test-mode signal TM1 of "0", the S-FF 200 enters a shift operation mode to take the serial input SI into the D-FF 207 in synchronization with the timing signal T.
With the shift-mode signal SM of "1" and the test-mode signal TM1 of "1", the S-FF 200 enters a test mode. In the test mode, supplying the comparison control signal CMP of "0" makes a test-invalid condition. The output of the comparator 201 forcedly becomes "1" and the Q-output of the D-FF 207 is fed back to the D-input to hold latch data of the D-FF 207.
In the test mode, supplying the comparison control signal CMP of "1" makes a test-valid condition. The input data D is compared with the expected value data EXP and when agrees, the EX-OR gate 202 outputs "0" and the comparator 201 outputs "1" as comparison result data to hold the latch data of the D-FF 207.
On the other hand, when disagrees, the EX-OR gate 202 outputs "1" and the comparator 201 outputs "0" as comparison result data to forcedly latch "0" into the D-FF 207 (to be reset).
FIG. 44 is a circuit diagram showing a configuration of a prior-art RAM with test circuit (showing only circuits connected to data outputs DO&lt;0&gt; to DO&lt;4&gt; of the RAM). As shown in FIG. 44, a test circuit 216 has a scan path for RAM test connecting in series five scan flip flops SFF&lt;0&gt; to SFF&lt;4&gt; each of which has the circuit configuration of FIG. 43. Hereinafter, the scan flip flop SFF&lt; &gt; is sometimes abbreviated as SFF&lt; &gt;.
Specifically, the SFF&lt;4&gt; externally receives serial input data SIDO as its serial input SI and its serial output SO is connected to a serial input SI of the SFF&lt;3&gt;, and the SFF&lt;2&gt;, the SFF&lt;1&gt; and the SFF&lt;0&gt; are connected in series likewise. A serial output SO of the last-stage SFF&lt;0&gt; is externally outputted as serial output data SODO.
The SFF&lt;0&gt; to SFF&lt;4&gt; receive the shift-mode signal SM, the test-mode signal TM1, the expected value data EXP, the comparison control signal CMP and the timing signal T in common. Further, the SFF&lt;0&gt; to SFF&lt;4&gt; receive data outputs DO&lt;0&gt; to DO&lt;4&gt; as respective input data D and output respective data outputs Q as data outputs Q&lt;0&gt; to Q&lt;4&gt;.
With reference to FIGS. 43 and 44, a RAM test operation will be discussed below.
(1) Prior to the RAM test, in the shift mode {TM1=0, SM=1}, the serial input data SIDO (the serial input SI of the SFF&lt;4&gt;) of "1" is sequentially shifted to latch "1" into all the SFF&lt;0&gt; to SFF&lt;4&gt;. At this time, clocks for five cycles are needed as the timing signal T. As a result, all the serial outputs SO&lt;0&gt; to SO&lt;4&gt; of the SFF&lt;0&gt; to SFF&lt;4&gt; become "1".
(2) In the test mode {TM1=1, SM=1}, the RAM test is executed on all the addresses. While test data are written or read out, the test-valid condition is made at a predetermined timing by appropriate control of the expected value data EXP and the comparison control signal CMP (when "1", comparison is made).
If a RAM 211 has a failure, the output DO&lt;i&gt; (i=0 to 4) of the RAM 211 disagrees with the expected value data EXP in the test-valid condition. At this time, the comparison result data from the comparator 201 in the SFF&lt;i&gt; is "0" and the SFF&lt;i&gt; latches "0" therein in synchronization with the clock signal T to be reset.
For example, when a failure is found in the SFF&lt;2&gt; connected to the output data DO&lt;2&gt; of the RAM 211, the serial output SO&lt;2&gt; becomes "0" (the serial outputs SO&lt;0&gt;, SO&lt;1&gt;, SO&lt;3&gt; and SO&lt;4&gt; are kept "1").
(3) In the shift mode {TM1=0, SM=1}, the test result is sequentially outputted as the serial output data SODO (the serial output SO of the SFF&lt;0&gt;).
In the above example, "1", "1", "0", "1" and "1" are outputted in this order as the serial output data SODO and the third serial output data SODO of "0" (indicative of failure) reveals existence of failure in the RAM 211.
Since the prior-art test circuit for RAM in the semiconductor integrated circuit device performs the failure test for RAM as above, through observation of the serial output data SODO which are externally outputted in the stage (2) in the test mode, whether there is a failure of the data output DO&lt;0&gt; can be detected but whether there is a failure of the other data outputs DO&lt;1&gt;, DO&lt;2&gt;, DO&lt;3&gt; and DO&lt;4&gt; can not be detected. Therefore, the test in the stage (2) needs recognition on whether there is a failure of all the data outputs DO&lt;0&gt; to DO&lt;4&gt; in the stage (3) after executing the test on the data outputs DO&lt;0&gt; to DO&lt;4&gt; of all the addresses. That disadvantageously requires longer time than necessary to perform a test for detecting a defective RAM.
FIG. 45 is a circuit diagram showing a configuration of a semiconductor integrated circuit device having a RAM with test circuit and a redundancy circuit. In FIG. 45, a RAM with test circuit has a configuration where the RAM 212 with test circuit of FIG. 44 is additionally provided with a redundancy circuit 213.
As shown in FIG. 45, the serial outputs SO&lt;1&gt; to SO&lt;4&gt; of the scan flip flops SFF&lt;1&gt; to SFF&lt;4&gt; are taken into a register 214 and stored as store data G&lt;1&gt; to G&lt;4&gt;.
The store data G&lt;1&gt; to G&lt;3&gt; of the register 214 are applied to respective ones of inputs of AND gates 221 to 223. The other input of the AND gate 221 is connected to an output of the AND gate 222, the other input of the AND gate 222 is connected to an output of the AND gate 223 and the other input of the AND gate 223 receives the store data G&lt;4&gt;. Outputs of the AND gates 221 to 223 are output data F&lt;1&gt; to F&lt;3&gt;.
Selectors 230 to 233 are provided correspondingly to the data outputs Q&lt;0&gt; to Q&lt;4&gt; (or data outputs DO&lt;0&gt; to DO&lt;4&gt;) of the RAM 212 with test circuit. The selectors 230 to 233 have "0"-inputs receiving data outputs Q&lt;0&gt; to Q&lt;3&gt;, "1"-inputs receiving the data outputs Q&lt;1&gt; to Q&lt;4&gt; and control inputs receiving the output data F&lt;1&gt; to F&lt;3&gt; and G&lt;4&gt;, respectively. Outputs of the selectors 230 to 233 are redundancy data outputs XDO&lt;0&gt; to XDO&lt;3&gt;, respectively.
On the other hand, an OR gate 215 and selectors 234 to 236 are provided correspondingly to the data inputs DI&lt;0&gt; to DI&lt;4&gt; of the RAM 212 with test circuit. One of inputs of the OR gate 215 receives an redundancy data input XDI&lt;0&gt; and the other receives the output data F&lt;1&gt;. The selectors 234 to 236 have "0"-inputs receiving redundancy data inputs XDI&lt;1&gt; to XDI&lt;3&gt;, "1"-inputs receiving the redundancy data inputs XDI&lt;0&gt; to XDI&lt;2&gt; and the control inputs receiving the output data F&lt;2&gt; and F&lt;3&gt; and the store data G&lt;4&gt;.
An output of the OR gate 215 is applied to the data input DI&lt;0&gt;, outputs of the selectors 234 to 236 are applied to the data inputs DI&lt;1&gt; to DI&lt;3&gt; and the redundancy data output XDO&lt;3&gt; is applied to the data input DI&lt;4&gt;.
With this configuration, if the data output DO&lt;2&gt; of the RAM 211, for example, has a failure, the SFF&lt;2&gt; corresponding to the data output DO&lt;2&gt; latches "0" indicative of failure therein. Specifically, the serial output SO&lt;2&gt; is "0" (the serial outputs SO&lt;0&gt;, SO&lt;1&gt;, SO&lt;3&gt; and SO&lt;4&gt; are kept "1").
When the serial outputs SO&lt;1&gt; to SO&lt;3&gt; are taken into the register 214, the store data G&lt;1&gt;=1, G&lt;2&gt;=0, G&lt;3&gt;=1 and G&lt;4&gt;=1 and the output data F&lt;3&gt;=1, F&lt;2&gt;=0 and FF&lt;1&gt;=0}. As a result, the redundancy data outputs XDO&lt;0&gt; to XDO&lt;3&gt; are outputted according to such a correspondence as {DO&lt;4&gt;/Q&lt;4&gt; to XDO&lt;3&gt;, DO&lt;3&gt;/Q&lt;3&gt; to XDO&lt;2&gt;, DO&lt;1&gt;/Q&lt;1&gt; to XDO&lt;1&gt; and DO&lt;0&gt;/Q&lt;0&gt; to XDO&lt;0&gt;} through the signal selection by the selectors 230 to 233. In short, the data output DO&lt;2&gt; having a failure is not used.
Similarly, the redundancy data inputs XDI&lt;0&gt; to XDI&lt;3&gt; are inputted according to such a correspondence as {XDI&lt;3&gt; to DI&lt;4&gt;, XDI&lt;2&gt; to DI&lt;3&gt; and DI&lt;2&gt;, XDI&lt;1&gt; to DI&lt;1&gt; and XDI&lt;0&gt; to DI&lt;0&gt;} through the signal selection by the selectors 234 to 236. In short, the redundancy data input XDI&lt;2&gt; is inputted also to the data input DI&lt;3&gt; besides the data input DI&lt;2&gt; corresponding to the data output DO&lt;2&gt; having a failure.
Thus, even when the RAM 211 provided with the data output DO&lt;2&gt; has a failure, it works normally as a 4-bit input/output RAM by using the RAM 212 with test circuit and the redundancy circuit 213 through connection change of the redundancy circuit 213.
When the D-FFs 207 in the SFF&lt;0&gt; the SFF&lt;4&gt; are not used as flip flops for output during a normal operation, the D-FFs 27 are used as registers for storing the redundancy control data in the redundancy circuit 213 to omit the register 214. Further, by omitting the OR gate 215, the data input DI&lt;0&gt; and the redundancy data input XDI&lt;0&gt; may be shorted as indicated by a broken line.
The prior-art redundancy circuit 213 needs logic circuits (the AND gates 221 to 223) for generating selection control signal output data F&lt;1&gt; to F&lt;3&gt;, being complicate in circuit configuration.